Venkata Sai Nithin Bazaru

MS in Computer Engineering at Texas A&M University

I am a Computer Engineering graduate student at Texas A&M University with a strong software engineering background and a focused interest in Design Verification, where software driven problem solving meets hardware correctness. I previously worked as a Software Engineer at Capgemini, building scalable backend and enterprise integration systems using object oriented design, rigorous testing, and cloud enabled architectures, experience that translates naturally to verification through structured testbenches, verification methodologies, and deep debugging. Through my graduate coursework, I am developing depth in VLSI with emphasis on hardware verification, Digital IC Design, Computer Architecture, and Design Verification is my primary career focus as it allows me to leverage my software foundation in OOP and system level thinking. I am actively seeking internship opportunities primarily in Design Verification, while remaining open to Software and Cloud Engineering roles that complement my background. Outside of engineering, I enjoy cooking, playing GeoGuessr, photography, playing cricket, watching movies, and listening to music.

bvsnithin412@tamu.edu bazaruvenkatasainithin@gmail.com

View Resume

Where I've Worked

Building scalable systems & driving impact

Texas A&M Libraries

Student Technician - Digital Collections

Dec 2025 - Present Part Time

University libraries' digital collections & repository. Supporting OAKTrust, command-line tooling, and ETD workflows.

Contributing to the development of command-line tools, assisting in design and implementation of features, writing unit tests, and ensuring robust functionality across tools

Supporting TAMU's institutional repository, OAKTrust, maintaining database integrity, managing metadata, and ensuring discoverability of collections documenting the university's scholarly output

Assisting with content submissions, responding to user inquiries, and managing permissions for electronic theses and dissertations using metadata schemas like Dublin Core

Tech Stack

Python OAKTrust Database DSpace JavaScript

Sports analytics & sponsorship prediction platform. Leading full-stack development, UI/UX, and R/Stata model validation.

Leading key technical initiatives from development to deployment for a professor-led sports analytics and sponsorship predictive platform

Spearheading UI/UX enhancements and backend optimizations to continuously improve platform performance and user experience

Updating and validating the core predictive model built in R, benchmarking its outputs against a closed-system Stata environment to ensure accuracy

Tech Stack

R Stata Python Full Stack

Capgemini (Client - John Lewis Partnership)

Senior Analyst/Software Engineer

Oct 2023 - Aug 2025 Full Time

Retail client (John Lewis). Building order processing and integration platforms at scale - automation, event-driven workflows, and cloud modernization.

Co-developed a mission-critical order processing platform in an Agile environment, replacing legacy systems to reliably process 1M+ weekly transactions with high availability

Automated the end-to-end supplier onboarding lifecycle, reducing processing time by 65% (from 14 to 5 days) and significantly enhancing operational efficiency through modern system integrations

Designed and implemented event-driven, hybrid integration workflows to enable near real-time data synchronization between modern services and legacy enterprise systems

Led technical evaluations for enterprise modernization, delivering comparative analysis that informed architectural decisions for cloud adoption and long-term web scalability

Tech Stack

webMethods Integration Java Spring/Spring Boot GCP Angular

Central Institute of Tool Design

VLSI Trainee

Feb 2022 - Mar 2022 Apprenticeship

VLSI R&D institute. Apprenticeship on high-speed Dadda multiplier design with Cadence tools and VHDL.

Completed an apprenticeship at CITD as a VLSI trainee, collaborating with faculty on a project titled "A High-Speed Design Technique for Dadda Multiplier"

Gained practical experience using Cadence tools and VHDL for digital circuit design and simulation

Developed a deeper understanding of high-speed arithmetic architecture implementation in VLSI environments

Tech Stack

VHDL Cadence VLSI Digital Design

My Education

Academic journey & qualifications

2025 - Present

Master of Science

Computer Engineering

Texas A&M University - College Station

Relevant Coursework

Computer Architecture Advanced Hardware Design Verification Intro to Hardware Design Verification Hardware Security Artificial Intelligence Software Engineering

2019 - 2023

Bachelor of Technology

Electronics & Communication Engineering

JNTU Hyderabad - Gokaraju Rangaraju Institute of Engineering and Technology

Relevant Coursework

Digital Electronics Microprocessors and Microcontrollers VLSI Design Integrated Circuits and Applications OOPS through Java Computer Architecture and Organization Cloud Computing Embedded System Design Probability Theory and Stochastic Processes

Featured Projects

Innovative solutions across hardware & software

Hardware Projects

HTAX Verification & Coverage Closure Using SystemVerilog & UVM

Built a UVM verification environment from scratch with constrained random sequences, assertions, and scoreboards, achieving 100% functional coverage through coverage driven verification.

UVM SystemVerilog

RTL Design & UVM Verification of AXI-Lite SRAM Controller

Designed the AXI-Lite SRAM controller RTL and its UVM verification environment using constrained random testing and regression analysis, achieving 96% functional coverage.

SystemVerilog UVM Verilog RTL

Octal Serial Peripheral Interface (OSPI) Verification Platform Development

Developed a UVM based verification platform for the Octal Serial Peripheral Interface using constrained random stimulus and functional coverage to ensure protocol compliance and design robustness.

SystemVerilog UVM Verilog RTL

Simple ALU Design & Verification

A SystemVerilog UVM-based verification environment for validating an Arithmetic Logic Unit (ALU).

SystemVerilog UVM Verilog RTL

Synchronous FIFO Design & Verification

A SystemVerilog UVM-based verification environment for validating a Synchronous FIFO.

SystemVerilog UVM Verilog RTL

View More on GitHub

Software Projects

Leet Planner

A group web application that aims to help students organize their daily study routines with a special focus on integrating LeetCode problem solving into their schedule.

Ruby Rails SQL

Collaborado

Collaborado is a collaborative platform for students to ask questions, share resources, and work together in real-time. Inspired by Piazza, it fosters interactive learning through discussion threads and resource sharing.

Ruby Rails SQL